1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to reducing power consumption within a flip-flop circuit on a semiconductor chip.
2. Description of the Relevant Art
The power consumption of modern complementary metal oxide semiconductor (CMOS) chips is proportional to the expression αfCV2, where the symbol α is the switching factor, or the probability a node will charge up or discharge during a clock cycle; f is the operations frequency of the chip; C is the equivalent load capacitance to be charged or discharged in a clock cycle; and the symbol V is the operational voltage of the chip. In order to reduce power consumption, one or more of these parameters may need to be reduced. However, reducing the operational frequency, f, also reduces the performance of the circuits on the chip. Therefore, this reduction is generally not desirable. Reducing the operational voltage, V, reduces the amount of current that may flow through a transistor and, thus, increases the propagation delays through transistors. If the threshold voltages are reduced in order to turn-on the transistors sooner and aid in maintaining performance, then transistor current leakage increases, which increases power consumption.
The last two terms α and C may be reduced by disabling portions of the chip during periods of non-use or by reducing transistor sizes. Also, some circuits that are used across the chip, rather than only in certain portions or blocks of the chip, may be investigated for power reduction techniques. One such circuit is the flip-flop circuit used for retaining state. The number of flip-flop circuits, which has reached the hundreds of thousands in modern designs, has been increasing with each generation of processors. The internal nodes of these circuits switch every clock cycle and, therefore, contribute to the total power consumption of the chip. One method of reducing the power consumption of flip-flop circuits is reducing the transistor sizes. However, a limit is reached when the transistors already have the minimum available channel width.
Another method to reduce the power consumption of flip-flop circuits is to use conditional techniques. These techniques disable the clock to the flip-flop circuits when the state of the flip-flop does not need to change. If the data input that meets the setup time to a flip-flop is the same as the already stored value within the flip-flop, then the output of the flip-flop is not going to change and the internal nodes do not need to switch during the subsequent clock cycle.
These conditional techniques allow the power consumption of flip-flop circuits to be reduced, but they may also require an exclusive or (XOR) type computation in order to verify the data input and the retained state have the same value. This added circuitry significantly increases the area of the flip-flop circuits and increases the number of gate delays for the data input to traverse within the flip-flop prior to the arrival of the clock edge.
In view of the above, efficient methods and mechanisms for reducing the power consumption of flip-flop circuits with a minimal additonal area and time delay are desired.